1. Field of the Invention
The present invention generally relates to material processing, especially processing of semiconductor materials for electronic devices and, more particularly, to etching processes and reaction vessels therefor.
2. Description of the Prior Art
The potential for improved performance and functionality of integrated circuits, as well as potential economies of manufacture, has driven integrated circuit designs to smaller regimes of minimum feature size or critical dimension (CD). While such reductions in feature size have resulted in stringent resolution requirements for lithography tools, some process variations have been increased to the point of seriously compromising manufacturing yields as feature sizes have decreased.
For example, it is conventional to form portions of electronic elements (e.g. transistors, capacitors and the like) using a plurality of semiconductor layers and to connect these elements in yet additional layers; each layer being separated from lower layers by a so-called interlayer dielectric (generally an oxide) having a nominal thickness through which connections called vias are selectively made. In practice, the thickness of the interlayer dielectric is not generally critical and is not typically varied significantly with the minimum feature size regime of the design. However, it can be readily understood that the transverse dimension of vias must generally correspond to the sizes of connections in the respective layers which will vary with the minimum feature size or critical dimension. Consequently, a reduction in minimum feature size or critical dimension generally corresponds to an increase of the height to width aspect ratio of the via.
In general, vias are formed by etching in accordance with a resist or patterned mask (e.g. of nitride) through a chemical reaction with the insulator/oxide. The reactive material is generally provided as ions in a plasma and the etch rate, which must be relatively high for commercially acceptable throughput, is generally proportional to the number of ions or reactive species which are incident on the surface to be etched. Therefore, high density plasmas are of substantial interest at the present time. However, as the aspect ratio of a via increases as etching proceeds, the relatively random trajectories of ions in a plasma causes the number of ions incident on the surface being etched to vary; resulting in variation in etch rate even between different locations on a wafer. Overetching may damage underlying structures and under etching may not allow a connection to be formed when conductive material is deposited inside the via.
The etch rate is further complicated by the complex reactions which may occur in a reaction vessel and which may involve the vessel itself or contaminants and/or reaction products that may be deposited thereon. Such materials may also become dislodged as particulates and contaminate the wafer being processed while their formation and reactions with the vessel may alter concentrations of reactant species and alter the chemical reactions and relative rates of those reactions taking place in the vessel. It is, of course, desirable to be able to control the reaction in a stable fashion based on as few parameters as possible and preferably only process parameters which are fully controllable such as reactant gas flow rate (and, secondarily, temperature). In practice, such process stability can seldom be obtained due to the complexity of side reactions, varying concentrations of byproducts and lack of accurate temperature control over the entirety of significant dimensions and volume of the reactor vessel.
For example, fluorocarbon gas is often used as a source of highly reactive fluorine ions which leave byproduct carbon ions that tend to form polymers and deposit on relatively cooler surfaces on the interior of the reactor vessel and the workpiece. (Carbon, in particular, may form compounds and/or allotropes which may result in deposits having unpredictable electrical characteristics or alloys which may significantly alter electrical characteristics of other structures.) In general, while measures are taken to maintain a constant and predetermined temperature in the reactor vessel, the temperature of the interior and regions thereof as well as the wafer may vary significantly in practice. Therefore, as the etching proceeds, polymer must be etched from the wafer along with the oxide. Because the etch rate in the vias diminishes with depth (and aspect ratio), an equilibrium between etching and deposition of polymer may be reached and no net further etching can be achieved. This condition is referred to as “etch-stop”.
(As used hereinafter, “etch-stop”, referring to the above-described equilibrium condition, is to be understood as distinguished from the similarly referenced “etch stop” structure such as a nitride underlying an oxide during an etch process selective thereto. Accordingly, while usage in the art may not be entirely consistent, a hyphenated term will be used to differentiate this condition from the similarly referenced structure. Usage as a verb form as opposed to a noun, often with an associated article such as “an etch stop” may differentiate the terms, as well.)
In an effort to more closely regulate side reactions with the reactor vessel and materials that may be deposited thereon, it is the current practice to periodically subject the reactor vessel to cleaning processes (such as “wetstrips”). Many differing processes for the purpose are known and may be used singly or in combination to remove contaminant materials. So-called seasoning processes may be included in an effort to increase resistance to contaminant deposition or resistant to chemical reaction of the reactor vessel and/or the potential contaminants. However, such processes are costly, especially in terms of tool down-time and are only marginally effective. Premature maintenance, reduced useful lifetime of the reactor vessel, increased wetstrip process costs and processing variability are disadvantages of conventional reactor chambers and manufacturing processes (especially etching processes) practiced in reactor chambers.
In this regard, it should be appreciated that 8000 Angstroms is substantially less than the desirable thickness of interlayer dielectrics at the present state of the art and 15000 Angstroms is marginal for reliable formation of via connections. This relatively wide variation in etch-stop depth also reflects a wide variation in etch rate precluding use of a timed etch process for via depth control (thus requiring more expensive alternatives such as optical emission spectroscopy (OES) for determining process completion) and an instability of control by reactant gas flow rate.
Use of other reactant gases present problems in developing high etch rates and throughput comparable to those available from polymer-forming fluorocarbon gases due to lower reactive ion density, lower reactivity of the ions and/or other effects. While reduced voltages are being used to operate integrated circuits in order to reduce heat dissipation, reduced thickness of interlayer dielectric may compromise dielectric film integrity and potentially impose severe design constraints (to avoid breakdown) if higher voltages are desired in any portion of the chip.
Therefore, it is seen that the development of equilibrium etch-stop conditions may severely compromise manufacturing yield at reduced CDs essential for increased integration density and limits reliable manufacture of integrated circuits at minimum feature size regimes which are otherwise supported by current lithographic techniques and resolution. However, at the present state of the art, there are no economically practical alternatives which allow reliable manufacture of integrated circuits with small CDs at a cost comparable to larger CD regimes.
There continue to be shortcomings with high density plasma (HDP) etch tool process stability with regard to critical dimensions (CD) and etch-stop depth variability due to chamber conditioning. HDP tools show significant issues with foreign material, shallow etch depth and CD matching issues. Foundry technologies drive contact aspect ratios higher than nominal etch depth performance of the chamber. Variability between wetstrips leads to contact opens and scrap. Variability in etch performance leads to premature chamber maintenance.